1. Field of the Invention
The present invention relates to a solid-state imaging device and a method for driving the same, and in particular to a solid-state imaging device usable as an imaging device for a digital still camera, a video camera or the like, and a method for driving the same.
2. Description of the Related Art
Recently, the image quality of digital still cameras has been rapidly enhanced. As an imaging device therefor, solid-state imaging devices, especially CCD image sensors having a pixel number of one million or greater have been widely used. These CCD image sensors are generally switchable between two driving modes, i.e., a still mode in which a signal charge is independently read from all the pixels so as to obtain a still picture, and a monitoring mode in which a moving picture is displayed on a liquid crystal monitor or the like.
In order to realize the function of the monitoring mode, a frame rate of about 30 frames per second is considered to be required. However, there is a limit in the driving frequency characteristics of a CCD image sensor, and a low power consumption is demanded. Therefore, it in not easy to raise the driving frequency. This makes it difficult to obtain the necessary frame rate in the monitoring mode as the number of pixels of a CCD image sensor increases.
In order to solve this problem, CCD image sensors having a pixel number of one million or greater currently adopt a method of increasing the frame rate by reading a signal charge only from a part of the pixels arranged in a vertical direction to remove data of some of the lines and thus reducing the data amount.
Another method for reducing the data amount in the vertical direction has also been proposed. This method will be described with reference to FIG. 21.
FIG. 21 in a plan view of a conventional CCD image sensor 100 as an exemplary conventional solid-state imaging device. The CCD image sensor 100 is of an interlace system and has four-phase driving vertical transfer registers.
The CCD image sensor 100 includes a plurality of photodiodes 101 each acting as a light receiving section, a plurality of transfer gates 102 provided in correspondence with the plurality of photodiodes 101 respectively, a plurality of vertical transfer registers 103, a horizontal transfer register 104, a charge detection section 105, an output amplifier 106, and a sweep-out drain 107.
The plurality of photodiodes 101 are arranged in a matrix in rows and columns on a semiconductor substrate. On the top surface of each of the photodiodes 101, an R, G or B color filter is provided. The RGB color filters are arranged in the Bayer pattern. Each of the photodiodes 101 generates an electric charge in response to receiving light. In this specification, the electric charge is also referred to as the “signal charge”. The charge represents data.
Each of the vertical transfer registers 103 is provided adjacent to a corresponding column of the photodiodes 101. Each vertical transfer register 103 is connected to the corresponding photodiodes 101 via the corresponding transfer gates 102. Each vertical transfer register 103 transfers the signal charge read from the photodiodes 101 in a vertical direction by the four-phase driving of φV1 through φV4.
The horizontal transfer register 104 is provided perpendicular to the vertical transfer registers 103. The horizontal transfer register 104 transfers the signal charge which has been transferred by each of the vertical transfer registers 103 in a horizontal direction by two-phase driving of φH1 and φH2. A signal charge transferred by the horizontal transfer register 104 is detected by the charge detection section 105 and output by the output amplifier 106.
The sweep-out drain 107 is provided adjacent to the horizontal transfer register 104. The sweep-out drain 107 discharges unnecessary charges row by row, so that the data of come unnecessary rows of the plurality of rows arranged in the vertical direction can be removed.
A method for reducing the data amount in the horizontal direction in order to raise the frame rate will be described with reference to FIG. 22.
FIG. 22 is a plan view of a conventional CCD image sensor 200 as another exemplary conventional solid-state imaging device. The CCD image sensor 200 is of an interlace system and has four-phase driving vertical transfer registers.
The CCD image sensor 200 includes a plurality of photodiodes 201 each acting as a light receiving section, a plurality of transfer gates 202 provided in correspondence with the plurality of photodiodes 201 respectively, a plurality of vertical transfer registers 203, a horizontal transfer register 204, a charge detection section 205, an output amplifier 206, a sweep-out drain 207A provided between a specified vertical transfer register 203 and the horizontal transfer register 204 for discharging unnecessary charges, and a control gate 208 for controlling the discharge of the charges performed by the sweep-out drain 207A.
The control gate 208 is controlled so as to allow the sweep-out drain 207A to discharge charges, so that the transfer of the signal charges from the specified vertical transfer register 203 to the horizontal transfer register 204 is prevented. Therefore, unnecessary data is removed in the horizontal direction, and the frame rate can be raised.
Another method for reducing the data amount in the horizontal direction will be described regarding a CCD image sensor 300 shown in FIG. 23 as another exemplary conventional solid-state imaging device. This method does not sweep data, but removes unnecessary data by adding signals from the light receiving sections for the same color in the same row.
FIG. 23(a) shows the initial state. In FIG. 23(b) showing the state after the first data read, data 301a has been read from a photodiode 301 for red and data 301b has been read from a photodiode 301 for green to a horizontal transfer register 304 via corresponding vertical transfer registers 303.
Then, as shown in FIG. 23(c), the data 301a and 301b, which were red in the first data read from the photodiodes 301 are transferred by two column by the horizontal transfer register 304.
In FIG. 23(d) showing the state after the second data read, data 301c has been read from a photodiode 301 for red and data 301d has been read from a photodiode 301 for green to the horizontal transfer register 304 via corresponding vertical transfer registers 303. The data read by the second data read is added to the data for the same color which was read by the first data read. Specifically, the data 301c for red is added to the data 301a for red, and data 301d for green is added to the data 301b for green.
Then, as shown in FIG. 23(e), the data corresponding to each photodiode 301 is transferred by one row in the vertical direction by the vertical transfer registers 303.
As shown in FIG. 23(f), the data 301a, the data 301b, the data 301c and the data 301d are transferred in the horizontal direction by the horizontal transfer register 304, and the signal charges are output from an output amplifier 306 via a charge detection section 305.
In this manner, unnecessary data is removed in the horizontal direction, and the frame rate is raised.
In the CCD image sensor 300, the color filters are generally arranged such that two adjacent filters in the horizontal direction are not of the same color. Once a signal is read from one of the vertical transfer registers 303 to the horizontal transfer register 304, signals corresponding to the same color cannot be added together. In order to allow signals (data) of the same color to be added together, the data read is performed as follows. As shown in FIG. 23, the data read from the vertical transfer registers 303 to the horizontal transfer register 304 performed in a plurality of stages. After data read in performed once from the vertical transfer register 303 to the horizontal transfer register 304 and before the data read is performed the next time from the vertical transfer register 303 to the horizontal transfer register 304, the signals which have been read are moved to the vertical column having the same color of data at the bottom (horizontal transfer). The horizontal transfer is repeated.
Solid-state imaging devices operating in such a manner are disclosed in, for example, Japanese Laid-Open Publication No. 11-54741 and Japanese Laid-Open Publication No. 2000-115643.
The solid-state imaging device disclosed in Japanese Laid-Open Publication No. 11-54741 has a three-layer transfer electrode between the vertical transfer registers and the horizontal transfer register. While some of the signal charges are held in the transfer electrode section, the other signal charges are first transferred to the horizontal transfer register. Then, the remaining signal charges are transferred to the horizontal transfer register. Thus, the newly transferred signal charges can be added to the first transferred signal charges.
The solid-state imaging device disclosed in Japanese Laid-Open Publication No. 2000-115643 includes a two-layer transfer electrode between the vertical transfer registers and the horizontal transfer register. The transfer number (the number of times that the signal is applied to a register which is necessary for the signal charge transferred by the register arrives at the horizontal transfer register) is different among different vertical transfers. The signal charges of pixels which are in the same row and are not adjacent to each other are sequentially transferred from the corresponding vertical transfer register to the horizontal transfer register. Thus, a signal charge which is transferred later in added to a signal charge first transferred.
The above-described conventional methods for removing unnecessary data can realize highly free data removal in the vertical direction. For data removal in the horizontal direction, the methods have the following problems.
In the structure shown in FIG. 22, the sweep-out drain 207A for discharging unnecessary charges and the control gate 208 for controlling the discharge of the charges are provided. Due to the progressing reduction in chip size and the progressing reduction in pixel size owing to increasing pixel density, it is inevitable to desire to provide the sweep-out drain 207A in a narrow area between the vertical transfer registers 203 and the horizontal transfer register 204. This is very difficult. In the case where the sweep-out drain 107 is provided adjacent to the horizontal transfer register 104, no problem is caused by the reduction in the pixel size since there is still a sufficient space adjacent to the horizontal transfer register 104. However, in this case, the discharge operation of the charges is performed at a time, unnecessary data in the horizontal direction cannot be selectively removed.
In order to perform the method of adding the signals of the some color which are adjacent in the horizontal direction with the conventional data removal methods, it is necessary to control the signal read from the vertical transfer registers to the horizontal transfer register column by column, such that there in a delay in the time to read the signals.
However, Japanese Laid-Open Publication No. 11-54741 only shows a structure for providing a time difference between times at which data is read from different vertical transfer registers. In addition, the solid-state imaging device disclosed in this publication requires a three-layer electrode, which complicates the production process. Japanese Laid-Open Publication No. 2000-115643 only shows a structure for providing a time difference between times at which data is read from different vertical transfer registers. In addition, in the solid-state imaging device disclosed in this publication, the number of phases of the two-layer electrode forming each vertical transfer register is different column by column. Therefore, the structure of the solid-state imaging device is complicated.